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INTEGRATED CIRCUITS
74F651A/74F652A Transceivers/registers
Product specification
Replaces datasheet 74F651/74F652/74F651A/74F652A of 1990 Oct 23
1999 Jun 23
IC15 Data Handbook
Philips Semiconductors
Philips Semiconductors
Product specification
Transceivers/registers
74F651A Octal transceiver/register, inverting (3-State) 74F652A Octal transceiver/register, non-inverting (3-State)
FEATURES
74F651A/74F652A
* Combines 74F245 and two 74F374 type functions in one chip * High impedance base inputs for reduced loading (70A in high
and low states)
DESCRIPTION
The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OEAB, OEBA) and select (SAB, SBA) pins are provided for bus management.
* Independent registers for A and B buses * Multiplexed real-time and stored data * Choice of non-inverting and inverting data paths * 3-State outputs * Industrial temperature range available (-40C to +85C) for
74F652A TYPE 74F651/74F652 74F651A/74F652A TYPICAL fmax 110MHz 175MHz
TYPICAL SUPPLY CURRENT( TOTAL) 140mA 110mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F651AN, N74F652AN N74F651AD, N74F652AD INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F652AN I74F652AD PKG DWG #
24-pin plastic slim DIP (300mil) 24-pin plastic SOL
SOT222-1 SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 - A7, B0 - B7 CPAB, CPBA SAB, SBA OEAB, OEBA A0 - A7, B0 - B7 A0 - A7, B0 - B7 A0 - A7, B0 - B7 A, B inputs A-to-B, B-to-A clock inputs A-to-B, B-to-A select inputs A-to-B, B-to-A output enable inputs A, B outputs for N74F651, N74F652 A, B outputs for N74F651A, N74F652A A, B outputs for I74F652A DESCRIPTION 74F (U.L.) HIGH/LOW 3.5/0.116 1.0/0.033 1.0/0.033 1.0/0.033 750/106.7 750/80 750/60 LOAD VALUE HIGH/LOW 70A/70A 20A/20A 20A/20A 20A/20A 15mA/64mA 15mA/48mA 15mA/36mA
Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
1999 Jun 23
2
853-1126 21852
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
PIN CONFIGURATION
74F651A
CPAB 1 SAB 2 OEAB 3 A0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 GND 12 24 VCC
LOGIC SYMBOL
74F651A
4 23 CPBA 22 SBA 21 OEBA 20 B0 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 20 VCC = Pin 24 GND = Pin 12 19 18 17 16 15 14 13 1 2 3 23 22 21 A0 A1 A2 A3 A4 A5 A6 A7 CPAB SAB OEAB CPBA SBA OEBA B0 B1 B2 B3 B4 B5 B6 B7 5 6 7 8 9 10 11
SF00401
SF00402
IEC/IEEE SYMBOL
74F651A
21 3 23 22 1 2 EN1 [BA] EN1 [AB] G3 G5 C6 G7 1 1 6D 5 6 7 8 9 10 11 1 7 7 20
LOGIC DIAGRAM
OEBA OEAB CPBA SBA CPAB SAB 21 3 23 22 1 2
74F651A
I of 8 channels
1D C1
4
5 5 1 2 1
4D
A0 19 18 17 16 15 14 13
4 1D C1
20 B0
SF00403
VCC = Pin 24 GND = Pin 12
to 7 other channels
SF00404
1999 Jun 23
3
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
PIN CONFIGURATION
74F652A
CPAB 1 SAB 2 OEAB 3 A0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 GND 12 24 VCC 23 CPBA 22 SBA 21 OEBA 20 B0 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6
LOGIC SYMBOL
74F652A
4 5 6 7 8 9 10 11
A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 23 22 21 CPAB SAB OEAB CPBA SBA OEBA B0 B1 B2 B3 B4 B5 B6 B7
20 13 B7 VCC = Pin 24 GND = Pin 12
19
18
17
16
15
14
13
SF00405
SF00406
IEC/IEEE SYMBOL
74F652A
21 3 23 22 1 2 EN1 [BA] EN1 [AB] G3 G5 C6 G7 1 1 6D 5 6 7 8 9 10 11 1 7 7 5 5 1 2 19 18 17 16 15 14 13 1 20
LOGIC DIAGRAM
OEBA OEAB CPBA SBA CPAB SAB 21 3 23 22 1 2
74F652A
I of 8 channels
1D C1
4
4D
4 A0 1D C1 20 B0
to 7 other channels
SF00407
SF00408
1999 Jun 23
4
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74F651A and 74F652A. The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins determine the direction of the data flow.
BUS MANAGEMENT FUNCTIONS
REAL TIME BUS TRANSFER BUS B TO BUS A REAL TIME BUS TRANSFER BUS A TO BUS B STORAGE FROM A, B, OR A AND B TRANSFER STORED DATA TO A AND/OR B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
OEAB OEBA CPAB CPBA SAB SBA L L X X X L
OEAB OEBA CPAB CPBA SAB SBA H H X X L X
OEAB OEBA CPAB CPBA SAB SBA X L L H X H X X X X X X X X
OEAB OEBA CPAB CPBA SAB SBA H L H or L H or L H H
SF00409
FUNCTION TABLE
INPUTS OEAB L L X H L L L L H H H H OEBA H H H H X L L L H H L L CPAB H or L H or L X X X H or L H or L H or L CPBA H or L H or L X H or L X X H or L H or L SAB X X X L X X X X L H H H SBA X X X X X L L H X X H H An Input Input Input Input Unspecified* Output Output Output Input Input Output Output DATA I/O Bn Input Input Unspecified* Output Input Input Input Input Output Output Output Output OPERATING MODE 74F651A Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real time B data to A bus Stored B data to A bus Real time A data to B bus Stored A data to B bus Stored A data to B bus Stored B data to A bus 74F652A Isolation Store A and B data Store A hold B Store A in both registers Hold A, store B Store B in both registers Real time B data to A bus Stored B data to A bus Real time A data to B bus Stored A data to B bus Stored A data to B bus Stored B data to A bus
Notes to function table 1. H = High-voltage level 2. L = Low-voltage level 3. * = The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition of the clock. 4. = Low-to-high clock transition 5. X = Don't care
1999 Jun 23
5
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range. SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range Commercial range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 72 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA C C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIk IOH IO OL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level Low level output current Operating free air temperature range Commercial range Industrial range (74F652A only) Commercial range Industrial range (74F652A only) 0 -40 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -15 48 36 +70 +85 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA mA C C
1999 Jun 23
6
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX MAX, VIH = MIN others A0-A7, B0-B7 OEAB, OEBA, CPAB, CPBA, SAB, SBA OEAB, OEBA, CPAB, CPBA, SAB, SBA A0-A7, B0-B7 A0-A7, B0-B7 IO = -3mA 3mA OH IOH = -15mA IO = MAX OL 10%VCC 5%VCC 10%VCC 10%VCC 5%VCC 0.42 -0.73 LIMITS MIN 2.4 2.7 2.0 0.55 0.55 -1.2 100 1 20 3.3 TYP2 MAX UNIT V V V V V V A mA A
VOH
High-level output voltage
VO OL VIK II
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current
VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = 5.5V, VI = 5.5V VCC = MAX, VI = 2.7V
IIH
IIL IOZH + IIH IOZL + IIL IO ICC
Low-level input current Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Output current3
VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX, V0 = 2.25V -60 105 115 115
-20 70 -70 -160 145 165 160
A A A mA mA mA mA
ICCH Supply current (total) ICCL ICCZ
VCC = MAX VCC = MAX VCC = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. IO is tested under conditions that produce current approximately one half of the true short-circuit output current (IOS).
1999 Jun 23
7
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
AC ELECTRICAL CHARACTERISTICS FOR 74F651A
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CPAB or CPBA to An or Bn Propagation delay An or Bn to Bn or An Propagation delay SAB or SBA to An or Bn Output enable time OEAB or OEBA to An or Bn Output disable time OEAB or OEBA to An or Bn Waveform 1 Waveform 1 Waveform 2, 3 Waveform 2, 3 Waveform 7, 8 Waveform 7, 8 155 4.5 5.5 2.5 4.0 4.0 5.0 3.0 3.5 1.5 2.5 TYP 175 7.0 7.5 4.5 6.5 7.0 7.0 5.0 6.0 4.0 6.0 10.0 10.5 7.5 9.0 10.0 10.0 8.0 8.5 7.0 8.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 140 4.0 5.0 2.0 4.0 3.5 4.5 2.5 3.0 1.0 2.0 11.0 11.0 8.5 10.0 12.0 10.0 8.5 9.0 7.5 9.0 MAX ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS FOR 74F651A
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) Setup time, high or low An or Bn to CPAB or CPBA Hold time, high or low An or Bn to CPAB or CPBA Setup time, high or low OEBA to OEAB or OEAB to OEBA Hold time, high or low OEBA to OEAB or OEAB to OEBA Pulse width, high or low CPAB or CPBA Waveform 4 Waveform 4 Waveform 5, 6 Waveform 5, 6 Waveform 1 3.5 4.0 0 0 5.0 5.0 0 0 4.5 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.0 4.5 0 0 5.0 5.0 0 0 4.5 4.0 MAX ns ns ns ns ns UNIT
Note to AC setup requirements for 74F651A: 1. Setup time is to protect against surge current caused by enabling 16 outputs (48mA per output) simultaneously.
1999 Jun 23
8
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
AC ELECTRICAL CHARACTERISTICS FOR 74F652A
LIMITS TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CPAB or CPBA to An or Bn Propagation delay An or Bn to Bn or An Propagation delay SAB or SBA to An or Bn Output enable time1 OEAB or OEBA to An or Bn Output disable time OEAB or OEBA to An or Bn Waveform 1 Waveform 1 Waveform 1 Waveform 2, 3 Waveform 7, 8 Waveform 7, 8 155 5.0 5.0 4.0 3.0 4.5 4.0 3.0 3.5 1.5 2.5 TYP 175 7.5 7.0 6.0 5.0 7.0 8.0 5.0 6.0 4.0 6.0 10.0 10.0 9.0 8.0 10.0 10.0 8.0 8.5 7.0 8.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 140 4.5 4.5 3.5 2.5 4.0 4.0 2.5 3.0 1.0 2.0 11.5 10.5 10.0 8.5 11.0 11.5 8.5 9.0 7.5 9.0 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 140 4.5 4.5 3.5 2.5 4.0 4.0 2.5 3.0 1.0 2.0 11.5 10.5 10.0 8.5 11.0 11.5 8.5 9.0 7.5 9.0 MAX ns ns ns ns ns ns
SYMBOL
PARAMETER
UNIT
AC SETUP REQUIREMENTS FOR 74F652A
LIMITS TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) Setup time, high or low An or Bn to CPAB or CPBA Hold time, high or low An or Bn to CPAB or CPBA Setup time, high or low OEBA to OEAB or OEAB to OEBA Hold time, high or low OEBA to OEAB or OEAB to OEBA Pulse width, high or low CPAB or CPBA Waveform 4 Waveform 4 Waveform 5, 6 Waveform 5, 6 Waveform 1 3.5 4.0 0 0 5.0 5.0 0 0 4.0 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.0 4.5 0 0 5.0 5.0 0 0 4.5 4.0 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.0 4.5 0 0 5.0 5.0 0 0 4.5 4.0 MAX ns ns ns ns ns
SYMBOL
PARAMETER
UNIT
Note to AC setup requirements for 74F652A 1. Setup time is to protect against surge current caused by enabling 16 outputs (48mA per output) simultaneously.
1999 Jun 23
9
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax CPBA or CPAB VM tw(H) tPHL VM VM tw(L) VM tPHL tPLH VM VM VM tPLH
An or Bn
VM
VM
SBA or SAB
An or Bn
Bn or An
An or Bn
SF00394
SF00395
Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency
Waveform 2. Propagation delay for An to Bn or Bn to An and SAB or SBA to An or Bn
An or Bn
VM tPLH
VM tPHL VM VM
SBA or SAB
An or Bn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L) VM
Bn or An
An or Bn
CPBA or CPAB
VM
SF00396
SF00397
Waveform 3. Propagation delay for An to Bn or Bn to An and SAB or SBA to An or Bn
Waveform 4. Data setup time and hold times
OEBA
VM tsu(L)
VM th(L) VM
OEAB
VM tsu(H)
VM th(H)
OEAB OEBA VM
SF00410
SF00411
Waveform 5. OEBA to OEAB setup time and hold times
Waveform 6. OEAB to OEBA setup time and hold times
OEBA VM OEAB tPZH An or Bn VM 0V tPHZ VOH -0.3V VM
OEBA VM OEAB tPZL An or Bn VM VOL +0.3V tPLZ VM
SF00412
SF00413
Waveform 7. 3-State output enable time to high level and output disable time from high level
Waveform 8. 3-State output enable time to low level and output disable time from low level
1999 Jun 23
10
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for Open Collector Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00128
1999 Jun 23
11
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
1999 Jun 23
12
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1999 Jun 23
13
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 06-99 Document order number: 9397 750 06142
Philips Semiconductors
1999 Jun 23 14

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